Employer will accept a Masters degree in Electrical Engineering, Computer Science, Engineering, Applied Sciences, Physics, or related field and 2 years of work experience in job offered or in an engineeringrelated occupation.br br Experience must include 6 months of experience in the followingbr br 1. System Verilog OVMUVM DV experience;br 2. Python, Perl, shell scripting;br 3. Assertions SVA or others;br 4. Digital ASICs design flows;br 5. Testbench Architecture;br 6. Coverage driven verification methodology; andbr 7. Object oriented programming
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